The present invention relates in general to fabrication of surfaces which are free of atomic steps to facilitate formation of submicron sized devices thereon.
Surface roughness of Si and other semiconductor wafer materials becomes increasingly important as characteristic dimensions of devices, such as FET's, optical devices and layered quantum well structures, are decreased. For example, individual atomic steps or bunches of steps on a wafer surface can have a significant effect on the local field, channel mobility and breakdown characteristics of devices having gate oxide thicknesses in the nanometer range. To avoid this problem, an atomic step-free region having lateral dimensions on the order of one micron is required to accommodate a typical device. Unfortunately, this requires an accuracy in orientation of better than 0.01.degree. over the entire wafer area; locating these regions would be a formidable task. Although high temperature annealing of nominally flat wafers can be used to reduce the root mean square roughness, in general it is impossible to insure entirely step-free regions at the desired locations of individual device structures. Previous work on clean Si(001) has indicated that at miscut angles below 0.03.degree., atomic steps may even be spontaneously generated to create "hill and valley" structures.